The present invention relates to a passivation layer in a semiconductor; and, more particularly, to a semiconductor with a stress reduction layer to prevent a passivation layer from being cracked during a packaging process and a manufacturing method therefor.
Generally, a passivation layer in a semiconductor acts as a protective coating to protect the underlying surface from physical and chemical reaction, e.g., scratch, corrosion, electro-dissolution, during a packaging process. Such passivation layer protects the semiconductor from being damaged by an environmental factor such as humidity. Such passivation layer is made of a combination of one or more oxide layers for stress reduction and one or more nitride layers for a protective coating.
For example, a plasma enhanced tetra ethyl ortho silicate (PETEOS) oxide layer is deposited on a substrate with a metal wiring by using the plasma enhanced chemical vapor deposition (PECVD) technique and further a SiH4 nitride layer is deposited over the PETEOS oxide layer by using the PECVD technique to form a passivation layer. Alternatively, a SiH4 oxide layer may be deposited by using the high density plasma (HDP) CVD technique and then a SiH4 nitride layer may be deposited over the SiH4 oxide layer by using the PECVD technique to form another passivation layer.
While a top metal wiring in a conventional semiconductor has a relatively thin thickness of about 5000 to 6000 angstroms, a top metal wiring in a semiconductor such as a multilayer wiring device or a power device has a thicker thickness of about 8000 to 10000 angstroms. Further, the top metal wiring in the power device extends to a wide region therein.
Such a passivation layer formed over the top metal wiring of the multiplayer wiring device or the power device may suffer from cracking, due to stress caused by an underlying metal wiring that are wide and thick. Therefore, there has been a long felt need for a stress resistant passivation layer having a low stress on the underlying metal wiring, as well as being robust to an external impact.
It is, therefore, an object of the present invention to provide a semiconductor with a stress reduction layer to prevent a passivation layer from being cracked during a packaging process and a manufacturing method therefor.
In accordance with one aspect of the present invention, there is provided a